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? semiconductor components industries, llc, 2006 june, 2006 ? rev. 4 1 publication order number NCP5318/d NCP5318 two/three/four?phase buck cpu controller the NCP5318 provides full ? featured and flexible control conforming to the intel ? vrm 10.1 specification for high ? performance cpus. the ic can be programmed as a two ? , three ? or four ? phase buck controller, and the per ? phase switching frequency can be as high as 1.0 mhz. combined with external gate drivers and power components, the controller implements a compact, highly integrated multi ? phase buck converter. enhanced v 2 ? control inherently compensates for variations in both line and load, and achieves current sharing between phases. this control scheme provides fast transient response, reducing the need for large banks of output capacitors and higher switching frequency. features ? switching regulator controller ? programmable 2/3/4 phase operation ? lossless current sensing ? enhanced v 2 control method provides fast transient response ? programmable up to 1.0 mhz switching frequency per phase ? programmable adaptive voltage positioning ? programmable soft ? start time ? current sharing ? differential current sense pins for each phase ? current sharing within 10% between phases ? protection features ? programmable latching overcurrent protection ? ?111110? and ?1 11111? dac code fault ? latched overvoltage protection ? undervoltage lockout ? external enable control ? three ? state mosfet driver control through drvon signal ? system power management ? 6 ? bit dac with 0.5% tolerance compatible with vrm 10.1 specification ? programmable lower power good threshold ? power good output with delay ? pre ? set no load offset voltage ? pb ? free package is available* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com a = assembly location wl = wafer lot yy = year ww = work week g= pb ? free package marking diagram i lim r osc v cc gate1 gate2 gate3 gate4 gnd v id2 v id3 v id4 pwrls v ffb ss pwrgd drvon v id1 v id0 v id5 enable cs2n cs2p cs1n cs1p sgnd v drp v fb comp cs4n cs4p cs3n cs3p pin connections (top view) device package shipping ? ordering information lqfp ? 32 ft suffix case 873a ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 2000 tape & reel NCP5318ftr2 lqfp ? 32 2000 tape & reel NCP5318ftr2g lqfp ? 32 (pb ? free) NCP5318 awlyywwg
NCP5318 http://onsemi.com 2 figure 1. 4 ? phase solution for vrm10.1: 120 a max, 101 a thermals, 1.4 vo, 400 khz, 1 m ll bst tg drn bg pgnd vs en co 1 2 3 7 8 5 6 4 12v_filter 12v_filter 21 gate1 25 cs1p cs1n 26 bst tg drn bg pgnd vs en co 1 2 3 7 8 5 6 4 12v_filter 12v_filter 20 gate2 27 cs2p cs2n 28 bst tg drn bg pgnd vs en co 1 2 3 7 8 5 6 4 12v_filter 12v_filter 19 gate3 16 cs3p cs3n 15 bst tg drn bg pgnd vs en co 1 2 3 7 8 5 6 4 12v_filter 12v_filter 18 gate4 14 cs4p cs4n 13 22 drvon 8 gnd + + ncp5355 NCP5318ftr2 2x ntd85n02rt4 1x ntd60n02rt4 vcc vid5 vid0 vid1 vid2 vid3 vid4 enable pwrgd sgnd pwrls vfb vffb vid5 vid0 vid1 vid2 vid3 vid4 vid_pwrgd vcc_pwrgd 17 u1 +3.3v +12v 30 31 32 29 1 2 3 7 9 4 5 11 10 12 vdrp comp rosc ss ilim rdrp 3.25k rs 15k rp 20k rfb 1.5k rf2* 15k ntc rf1 2k 1.5k rvcc 10 cvcc2 4.7 f cvcc1 0.1 f r1 2.2 c3 0.1 f c1 4.7 f c4 4.7 f r2 2.2 c2 4.7nf rs1 3.4k cs1 0.1 f 280nh d1 bat54ht1 bi tech hm00?02702 bi tech pa0343?1 2 1 4 3 12v_filter 2x2 header 6 power gnd signal gnd 24 23 5x 1000 f sanyo 16sa1000m 1 h css 0.1 f rf open ca1 tbd ra1 tbd cd1 1nf rd1 1k cf open ca2 4.7nf rgnd 0 rlim1 18.2k rlim2 35.5k 165a trip @ 1.25m * rf2 located near output inductors 10x 560 f sanyo sepc560m co2 16x 22 f vccp vssp cpu gnd gnd +12v
NCP5318 http://onsemi.com 3 maximum ratings rating value unit operating junction temperature 150 c lead temperature soldering, reflow (note 1) NCP5318ftr2 NCP5318ftr2g 230 peak 260 peak c storage temperature range ? 65 to 150 c esd susceptibility: human body model 2.0 kv jedec moisture sensitivity level NCP5318ftr2 NCP5318ftr2g 1 3 ? ? package thermal resistance: r ja 52 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. 60 second maximum above 183 c. maximum ratings pin number pin symbol v max v min i source i sink 1 ? 3, 30 ? 32 v id0 ? v id5 18 v ? 0.3 v 1.0 ma 1.0 ma 4 pwrls 7.0 v ? 0.3 v 1.0 ma 1.0 ma 5 v ffb 7.0 v ? 0.3 v 1.0 ma 1.0 ma 6 ss 7.0 v ? 0.3 v 1.0 ma 1.0 ma 7 pwrgd 18 v ? 0.3 v 1.0 ma 20 ma 8 drvon 7.0 v ? 0.3 v 1.0 ma 1.0 ma 9 sgnd 1.0 v ? 1.0 v 1.0 ma ? 10 v drp 7.0 v ? 0.3 v 1.0 ma 1.0 ma 11 v fb 7.0 v ? 0.3 v 1.0 ma 1.0 ma 12 comp 7.0 v ? 0.3 v 1.0 ma 1.0 ma 13 cs4n 18 v ? 0.3 v 1.0 ma 1.0 ma 14 cs4p 18 v ? 0.3 v 1.0 ma 1.0 ma 15 cs3n 18 v ? 0.3 v 1.0 ma 1.0 ma 16 cs3p 18 v ? 0.3 v 1.0 ma 1.0 ma 17 gnd ? ? 0.4 a 1.0 s, 100 ma dc ? 18 ? 21 gate4 ? gate1 18 v ? 0.3 v 0.1 a 1.0 s, 25 ma dc 0.1 a 1.0 s, 25 ma dc 22 v cc 18 v ? 0.3 v ? 0.4 a 1.0 s, 100 ma dc 23 r osc 7.0 v ? 0.3 v 1.0 ma 1.0 ma 24 i lim 7.0 v ? 0.3 v 1.0 ma 1.0 ma 25 cs1p 18 v ? 0.3 v 1.0 ma 1.0 ma 26 cs1n 18 v ? 0.3 v 1.0 ma 1.0 ma 27 cs2p 18 v ? 0.3 v 1.0 ma 1.0 ma 28 cs2n 18 v ? 0.3 v 1.0 ma 1.0 ma 29 enable 18 v ? 0.3 v 1.0 ma 1.0 ma
NCP5318 http://onsemi.com 4 electrical characteristics (0 c < t a < 70 c; v cc = 12 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 95.3 k , v(i lim ) = 1.0 v, dac code 010100; unless otherwise noted) voltage identification (vid) voltage identification bits (connect v fb to comp, measure comp) nominal voltage (v) min typ max units v id4 v id3 v id2 v id1 v id0 v id5 ? 0.5% no load +0.5% 0 1 0 1 0 0 0.8375 0.8144 0.8185 0.8226 v 0 1 0 0 1 1 0.8500 0.8268 0.8310 0.8352 v 0 1 0 0 1 0 0.8625 0.8393 0.8435 0.8477 v 0 1 0 0 0 1 0.8750 0.8517 0.8560 0.8603 v 0 1 0 0 0 0 0.8875 0.8642 0.8685 0.8728 v 0 0 1 1 1 1 0.9000 0.8766 0.8810 0.8854 v 0 0 1 1 1 0 0.9125 0.8890 0.8935 0.8980 v 0 0 1 1 0 1 0.9250 0.9015 0.9060 0.9105 v 0 0 1 1 0 0 0.9375 0.9139 0.9185 0.9231 v 0 0 1 0 1 1 0.9500 0.9263 0.9310 0.9357 v 0 0 1 0 1 0 0.9625 0.9388 0.9435 0.9482 v 0 0 1 0 0 1 0.9750 0.9512 0.9560 0.9608 v 0 0 1 0 0 0 0.9875 0.9637 0.9685 0.9733 v 0 0 0 1 1 1 1.0000 0.9761 0.9810 0.9859 v 0 0 0 1 1 0 1.0125 0.9885 0.9935 0.9985 v 0 0 0 1 0 1 1.0250 1.0010 1.0060 1.0110 v 0 0 0 1 0 0 1.0375 1.0134 1.0185 1.0236 v 0 0 0 0 1 1 1.0500 1.0258 1.0310 1.0362 v 0 0 0 0 1 0 1.0625 1.0383 1.0435 1.0487 v 0 0 0 0 0 1 1.0750 1.0507 1.0560 1.0613 v 0 0 0 0 0 0 1.0875 1.0632 1.0685 1.0738 v 1 1 1 1 1 1 off v 1 1 1 1 1 0 off v 1 1 1 1 0 1 1.1000 1.0756 1.0810 1.0864 v 1 1 1 1 0 0 1.1125 1.0880 1.0935 1.0990 v 1 1 1 0 1 1 1.1250 1.1005 1.1060 1.1115 v 1 1 1 0 1 0 1.1375 1.1129 1.1185 1.1241 v 1 1 1 0 0 1 1.1500 1.1253 1.1310 1.1367 v 1 1 1 0 0 0 1.1625 1.1378 1.1435 1.1492 v 1 1 0 1 1 1 1.1750 1.1502 1.1560 1.1618 v 1 1 0 1 1 0 1.1875 1.1627 1.1685 1.1743 v 1 1 0 1 0 1 1.2000 1.1751 1.1810 1.1869 v 1 1 0 1 0 0 1.2125 1.1875 1.1935 1.1995 v 1 1 0 0 1 1 1.2250 1.2000 1.2060 1.2120 v 1 1 0 0 1 0 1.2375 1.2124 1.2185 1.2246 v *vid code is for reference only. ?v out no load is the input to the error amplifier.
NCP5318 http://onsemi.com 5 electrical characteristics (0 c < t a < 70 c; v cc = 12 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 95.3 k , v(i lim ) = 1.0 v, dac code 010100; unless otherwise noted) voltage identification (vid) (continued) voltage identification bits (connect v fb to comp, measure comp) nominal voltage (v) min typ max units v id4 v id3 v id2 v id1 v id0 v id5 ? 0.5% no load +0.5% 1 1 0 0 0 1 1.2500 1.2248 1.2310 1.2372 v 1 1 0 0 0 0 1.2625 1.2373 1.2435 1.2497 v 1 0 1 1 1 1 1.2750 1.2497 1.2560 1.2623 v 1 0 1 1 1 0 1.2875 1.2622 1.2685 1.2748 v 1 0 1 1 0 1 1.3000 1.2746 1.2810 1.2874 v 1 0 1 1 0 0 1.3125 1.2870 1.2935 1.3000 v 1 0 1 0 1 1 1.3250 1.2995 1.3060 1.3125 v 1 0 1 0 1 0 1.3375 1.3119 1.3185 1.3251 v 1 0 1 0 0 1 1.3500 1.3243 1.3310 1.3377 v 1 0 1 0 0 0 1.3625 1.3368 1.3435 1.3502 v 1 0 0 1 1 1 1.3750 1.3492 1.3560 1.3628 v 1 0 0 1 1 0 1.3875 1.3617 1.3685 1.3753 v 1 0 0 1 0 1 1.4000 1.3741 1.3810 1.3879 v 1 0 0 1 0 0 1.4125 1.3865 1.3935 1.4005 v 1 0 0 0 1 1 1.4250 1.3990 1.4060 1.4130 v 1 0 0 0 1 0 1.4375 1.4114 1.4185 1.4256 v 1 0 0 0 0 1 1.4500 1.4238 1.4310 1.4382 v 1 0 0 0 0 0 1.4625 1.4363 1.4435 1.4507 v 0 1 1 1 1 1 1.4750 1.4487 1.4560 1.4633 v 0 1 1 1 1 0 1.4875 1.4612 1.4685 1.4758 v 0 1 1 1 0 1 1.5000 1.4736 1.4810 1.4884 v 0 1 1 1 0 0 1.5125 1.4860 1.4935 1.5010 v 0 1 1 0 1 1 1.5250 1.4985 1.5060 1.5135 v 0 1 1 0 1 0 1.5375 1.5109 1.5185 1.5261 v 0 1 1 0 0 1 1.5500 1.5233 1.5310 1.5387 v 0 1 1 0 0 0 1.5625 1.5358 1.5435 1.5512 v 0 1 0 1 1 1 1.5750 1.5482 1.5560 1.5638 v 0 1 0 1 1 0 1.5875 1.5607 1.5685 1.5763 v 0 1 0 1 0 1 1.6000 1.5731 1.5810 1.5889 v *vid code is for reference only. ?v out no load is the input to the error amplifier.
NCP5318 http://onsemi.com 6 electrical characteristics (0 c < t a < 70 c; v cc = 12 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 95.3 k , v(i lim ) = 1.0 v, dac code 010100; unless otherwise noted) characteristic test conditions min typ max unit vid inputs input threshold v id5 , v id4 , v id3 , v id2 , v id1 , v id0 400 600 800 mv vid pin current v id5 , v id4 , v id3 , v id2 , v id1 , v id0 = 0 v ? 0.2 1.0 a sgnd bias current sgnd < 300 mv, all dac codes 10 20 40 a sgnd voltage compliance range ? ? 200 ? 300 mv power good upper threshold, offset from no load set point 85 97 115 mv lower threshold constant pwrgds/no load set point 0.475 0.505 0.525 v/v output low voltage v ffb = 1.0 v, i pwrgd = 4.0 ma ? 0.18 0.40 v delay v ffb high to pwrgd high 1.0 2.0 4.0 ms overvoltage protection ovp threshold above vid ? 170 215 250 mv enable input start threshold gates switching, ss high ? ? 0.8 v stop threshold gates not switching, ss low 0.4 ? ? v hysteresis ? 100 170 ? mv input pull ? up voltage 1.0 m to gnd 2.7 2.9 3.3 v input pull ? up resistance ? 7.0 10 20 k error amplifier v fb bias current ? ? 0.1 1.0 a comp source current comp = 0.5 v to 2.0 v 40 70 100 a comp sink current ? 40 70 100 a transconductance (note 2) 1.1 1.3 1.5 mmho open loop dc gain (note 2) 72 80 ? db unity gain bandwidth c comp = 30 pf (note 2) ? 4.0 ? mhz psrr @ 1.0 khz (note 2) ? 60 ? db comp max voltage v fb = 0 v 2.4 2.9 ? v comp min voltage v fb = 1.6 v ? 80 150 mv pwm comparators minimum pulse width measured from csxp to gatex, v fb = csxn = 0.5, comp = 0.5 v, 60 mv step between csxp and csxn; measure at gatex = 1.0 v (note 2) ? 40 100 ns transient response time measured from csxn to gatex, comp = 2.1 v, csxp = csxn = 0.5 v, csxn stepped from 1.2 v to 2.0 v (note 2) ? 40 60 ns channel startup offset csxp = csxn = v fb = 0, measure vcomp when gatex switch high 0.35 0.62 0.75 v artificial ramp amplitude 50% duty cycle ? 175 ? mv mosfet driver enable (drvon) output high drvon floating 2.3 ? ? v output low i = 100 a ? ? 0.2 v pull ? down resistance drvon = 1.5 v, enable = 0 v, r = 1.5 v/i(drvon) 35 70 140 k source current drvon = 1.5 v 0.5 3.0 6.5 ma 2. guaranteed by design, not tested in production.
NCP5318 http://onsemi.com 7 electrical characteristics (continued) (0 c < t a < 70 c; v cc = 12 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 95.3 k , v(i lim ) = 1.0 v, dac code 010100; unless otherwise noted) characteristic unit max typ min test conditions gates high voltage measure gatex, i gatex = 1.0 ma 2.25 ? ? v low voltage measure gatex, i gatex = 1.0 ma ? 0.1 0.7 v rise time gate 0.8 v < gatex < 2.0 v, v cc = 10 v ? 5.0 10 ns fall time gate 2.0 v > gatex > 0.8 v, v cc = 10 v ? 5.0 10 ns oscillator switching frequency r osc = 95.3 k, 3 phase r osc = 95.3 k, 4 phase 276 213 325 251 374 289 khz r osc voltage ? 0.95 1.02 1.05 v phase delay, 3 phases v cc = cs4p = cs4n 100 120 140 deg phase delay, 4 phases ? 75 90 105 deg phase disable threshold v cc ? (cs4p = cs4n) 500 ? ? mv adaptive voltage positioning v drp output voltage to dac out offset csxp = csxn, v fb = comp, measure v drp ? comp ? 20 0 +20 mv current sense amplifier to v drp gain (each channel separately) csxp ? csxn = 80 mv, v fb = comp, mea- sure v drp ? comp for 25 c < t a < 70 c 4.37 4.6 4.83 v/v v drp source current ? 0.95 1.3 3.0 ma v drp sink current ? 0.2 0.4 0.6 ma soft ? start charge current ? 30 44 50 a discharge current ? 90 120 160 a comp pull ? down current ? 0.2 0.9 2.1 ma current sensing and overcurrent protection csxp input bias current csxn = csxp = 0 v ? 0.1 1.0 a csxn input bias current csxn = csxp = 0 v ? 0.1 1.0 a current sense amp to pwm gain csxn = 0 v, csxp = 80 mv, measure v(comp) when gatex switches high 3.4 4.6 5.8 v/v current sense amp to pwm bandwidth (note 2) ? 7.0 ? mhz current sense amp to i lim gain csxp ? csxn = 20 mv to 60 mv, ramp i lim until ss goes low 3.228 3.390 3.526 v/v current sense amp to i lim bandwidth (note 2) ? 1.0 ? mhz current limit filter slew rate (note 2) 2.0 5.0 13 mv/ s i lim input bias current i lim = 0 v ? 0.1 1.0 a current sense amp to i lim output offset t = 80 c ? 82 ? 12 58 mv current sense common mode input range (note 2) 0 ? 2.0 v general electrical specifications v cc operating current comp = 0.3 v (no switching) ? 27 35 ma uvlo start threshold ss charging, gatex switching 8.5 9.0 9.5 v uvlo stop threshold gatex not switching, ss and comp discharging 7.5 8.0 8.5 v uvlo hysteresis start ? stop 0.8 1.0 1.2 v 2. guaranteed by design, not tested in production.
NCP5318 http://onsemi.com 8 pin description pin no. pin symbol pin name description 1 ? 3, 30 ? 32 v id0 ? v id5 dac vid inputs vid ? compatible logic input used to program the converter output voltage. all high on v id0 ? v id4 generates fault. ? start ? start time. 8 drvon drive on logic high enables mosfet drivers, and logic low turns all mosfets off through mosfet drivers. pulled to ground through internal 70 k resistor. 10 v drp output of current sense amplifiers for adaptive voltage positioning the offset above dac voltage is proportional to the sum of inductor current. a resistor from this pin to v fb programs the amount of adaptive voltage positioning. leave this pin open for no adaptive voltage positioning. ? start and fault conditions. it is also the inverting input of pwm comparators. ? inverting input to current sense amplifier #4. ? inverting input to current sense amplifier #3, and phase 3 disable pin. ? 21 ? gate1 ? inverting input to current sense amplifier #1. ? inverting input to current sense amplifier #2. 29 enable enable a voltage less than the threshold puts the ic in fault mode, discharging ss. connect to system vid pwrgd signal to control powerup sequencing. hysteresis is provided to prevent chatter.
NCP5318 http://onsemi.com 9 figure 2. block diagram + ? + ? + ? + ? + ? reset dominant protections overvoltage fault current sense oscillator 6 ? bit dac error amp soft ? start power good 70 k comp 19 mv + ? 0.62 v + ? 3.3 v 10 k 0.7 v 0.5 v vfb ss vid4 vid3 vid2 vid1 vid0 vid5 sgnd vid4 vid3 vid2 vid1 vid0 vid5 ref dac 111111 fault ss clamp dac pwrls pgd pwrls enable rosc vffb cs1p cs1n cs2p cs2n cs3p cs3n cs4p cs4n cs1p cs1n cs2p cs2n cs3p cs3n cs4p cs4n gnd ilim vcc i_sum i_sum ilim vcore disable vcc_uvlo 111111 fault ov i1 i2 i3 i4 clk1 clk2 clk3 clk4 ramp4 ramp3 ramp2 ramp1 clk1 clk2 clk3 clk4 clk1 clk2 clk3 clk4 cs4p rosc comp vdrp pwrgd gate1 sq r gate2 sq r gate3 sq r gate4 sq r drvon
NCP5318 http://onsemi.com 10 typical performance characteristics figure 3. dac variation versus temperature figure 4. power good delay versus temperature temperature ( c) temperature ( c) figure 5. ovp threshold above vid versus temperature figure 6. channel startup offset versus temperature temperature ( c) temperature ( c) figure 7. oscillator frequency versus total r osc value dac variation from nominal (%) pwrgd delay (ms) ovp threshold (mv) average channel offset (mv) r osc (k ) switching frequency (khz) ? 0.50 ? 0.40 ? 0.30 ? 0.20 ? 0.10 0.00 0.10 0.20 0.30 0.40 0.50 0 20 40 60 80 100 120 vid = 010100 vid = 111101 vid = 101101 vid = 010101 0.00 0.50 1.00 1.50 2.00 2.50 3.00 0 20406080100120 205 210 215 220 225 230 235 240 245 0 20 40 60 80 100 120 400 450 500 550 600 650 700 0 20 40 60 80 100 120 100 1000 10 100 1000 3 phase mode 4 phase mode
NCP5318 http://onsemi.com 11 figure 8. switching frequency versus temperature (r osc = 95.3 k ) temperature ( c) 4 phase frequency (khz) 3 phase frequency (khz) 241 242 243 244 245 246 247 248 249 0 20 40 60 80 100 120 311 312 313 314 315 316 317 318 319 3 phase mode 4 phase mode figure 9. v rosc versus temperature figure 10. current sense to v drp gain versus temperature temperature ( c) temperature ( c) r osc voltage (v) cs to v drp gain (v/v) 1.015 1.016 1.017 1.018 1.019 0 20 40 60 80 100 120 4.50 4.55 4.60 4.65 4.70 4.75 0 20 40 60 80 100 120 figure 11. soft ? start charge current versus temperature figure 12. current sense amplifier to pwm gain versus temperature temperature ( c) temperature ( c) ss charge current ( a) current sense amp gain (v/v) 40 41 42 43 44 45 46 0 20 40 60 80 100 120 3.50 4.00 4.50 5.00 5.50 0 20 40 60 80 100 120
NCP5318 http://onsemi.com 12 typical performance characteristics figure 13. cs amp to i lim gain versus temperature figure 14. i lim offset versus temperature temperature ( c) temperature ( c) current sense to i lim gain (v/v) i lim offset (mv) 3.33 3.34 3.35 3.36 3.37 3.38 3.39 3.40 3.41 0 20 40 60 80 100 120 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 10 0 20 40 60 80 100 120 figure 15. v cc operating current versus temperature temperature ( c) i cc current (ma) 25.5 26.0 26.5 27.0 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 0 20 40 60 80 100 120
NCP5318 http://onsemi.com 13 figure 16. operating waveforms v cc enable v ref fault uvlo fault fault reset fault latch fault drvon ss comp v out i out pwrgd power ? on enabled startup normal operation overcurrent latch ? off power ? off to reset oc fault power ? on enabled startup uvlo power ? off to reset uvlo fault power ? on enabled startup overvoltage power ? off
NCP5318 http://onsemi.com 14 applications information overview the NCP5318 is a multiphase, synchronous buck controller using the enhanced v 2 topology which combines the fast transient response of the original v 2 topology with the load current sharing characteristic of peak current ? mode control. the NCP5318 can be operated as an interleaved two/three/four ? phase controller. differential current sensing is incorporated in order to more easily achieve effective current sharing. converter output is regulated to a voltage corresponding to the logic states at six digital inputs. the NCP5318 incorporates a power good (pwrgd) function, providing integrated fault monitoring and sequencing that simplifies design, minimizes circuit board area, and reduces overall system cost. fixed frequency multi ? phase control in a multi ? phase buck converter , multiple, synchronously rectified, buck power stages are connected in parallel and are energized at a common frequency but with staggered phasing (interleaving). each stage carries only part of the total output current. in four ? phase mode, each phase oscillator is delayed 360/4 ? or 90 ? degrees from that of the previous phase. likewise, for other phase counts, each phase oscillator is delayed 360/n degrees from that of the previous phase, where n is the number of phases. advantages of a multiphase converter over a single ? phase converter include a better heat distribution and decreased input and output ripple currents. breaking up heat into a greater number of smaller amounts, reduces pc board thermal stress. multiple phases also permits phase inductance to be higher than used in a single ? phase converter capable of equal transient response, with correspondingly lower phase ripple current and i 2 r losses. in addition to the higher efficiency, input capacitor current appears even lower because of the cancellation achieved by the summation of individual, phase shifted, ripple currents. this often allows the use of fewer input capacitors without exceeding the capacitor rms current rating. also due to the decrease in phase ripple current, output di/dt change from positive to negative during switching is reduced. this reduction of output di/dt change decreases the output capacitor esl component of output ripple voltage ? often allowing a reduction in the number of ceramic output capacitors. because the inductors are always connected between the output and some low impedance (either the input supply or ground), the ef fective inductance value seen at the output is the value of all inductors connected in parallel (the value of a single inductor divided by the number of phases). multiphase output current ramp ? up (+di/dt) or ramp ? down ( ? di/dt) exhibits finer granularity due to the summation of the smaller individual phase di/dt produced by the larger individual inductors. within one switching cycle, however, total converter di/dt can sum to the same di/dt as a power stage with a single inductor of the same effective value. enhanced v 2 control enhanced v 2 control measures and adjusts the output current in each phase while simultaneously adjusting the current of all phases to maintain the correct output voltage. enhanced v 2 responds to output voltage disturbances by the combined effect of two mechanisms. the first mechanism includes the response of the error amplifier, and is responsible for maintaining the dc accuracy of the output voltage setting. depending on the frequency compensation set by the amplifier?s external components, the error amplifier response begins to change the pwm duty cycle within one to two cycles. the second mechanism is the direct coupling of converter output voltage to all non ? inverting pwm comparator inputs, which dominates pwm response at frequencies above the unity ? gain crossover frequency of the compensated error amplifier. a rapid increase in load current that decreases converter output voltage immediately extends the duty cycle of any phase already on, and will typically increase the duty cycle of several of the following phases for one cycle. figure 17. enhanced v 2 control employing resistive current sensing and internal ramp + ? swnode lx rlx rsx csxp csa cox csxn + v out (v core ) ?fast ? feedback? connection + ? pwm comp to pwm latch reset channel startup offset ? + e.a. dac out v fb comp internal ramp + x = 1, 2, 3 or 4 v ffb + ?
NCP5318 http://onsemi.com 15 the NCP5318 provides a differential input (csxn and csxp) that accepts inductor current information for each phase as shown in figure 17. the triangular inductor current is measured across r s and amplified before being summed with the channel startup offset, the internal ramp and the output voltage. the internal ramp provides greater design flexibility by allowing smaller external (current) ramps, lower minimum pulse widths, higher frequency operation and pwm duty cycles above 50% without external slope compensation. when the controller is enabled, gatex output (gate output of any phase) transitions to a high voltage at the start of the oscillator cycle for that phase, commanding a power stage to switch on. inductor current in that power stage then ramps up until the combination of startup offset voltage, its current sense signal, its internal ramp and the output voltage ripple exceed the compensated feedback signal at the other pwm comparator input. this brings gatex low, which commands that power stage off. while gatex is high, the enhanced v 2 control circuit will respond to line and load variations, but once gatex is low, that phase cannot respond until the next start of its oscillator cycle. therefore, the NCP5318 will take, at most, the off ? time of the oscillator to respond to disturbances. with multiple phases, the time to respond to disturbances is significantly reduced due to the increased likelihood of a gatex being high, and closer average proximity of oscillator starts, however the magnitude of that response (for equivalent total inductance) is equivalently reduced. turn on of a phase with higher inductor current will terminate the pwm cycle earlier, providing negative feedback. current sharing is accomplished by referencing the pwm comparators of all phases to the same error amplifier signal (comp pin). error amplifier output (comp) voltage no load bias point as shown in figure 17, the voltage present at each pwm comparator?s non ? inverting input is the sum of the channel startup offset, output voltage, and the inductor current and internal ramps corresponding to that phase. when the average output current is zero, the error amplifier output at the comp pin will be: v comp v out channel_startup_offset int_ramp g csa ext_ramp 2 int_ramp is the fraction of th e internal ramp (?artificial ramp amplitude? = 100 mv at a 50% duty cycle) corresponding to the steady state duty cycle, ext_ramp is the peak ? to ? peak external steady ? state current ramp appearing across csxp to csxn, g csa is the current sense amplifier gain (?current sense amp to pwm gain? = 3.0 v/v). when the technique known as ?lossless inductor current sensing? is used as in figure 19, the ma gnitude of ext_ramp is: ext_ramp d (v in v out ) (r csx c csx f sw ) where d is duty cycle expressed as a fraction. for example, if v out at zero load is set to 1.480 volts and the input voltage v in is 12.0 v, the duty cycle (d) will be 1.480/12.0 or 12.3%. int_ramp will be 100 mv/50% x 12.3% = 25 mv. realistic values for r csx , c csx and f sw are 2.5 k , 0.1 f and 350 khz. using these and the previously mentioned formula, ext_ramp will be 14.8 mv. v comp 1.480 v 0.60 v 25 mv 3.0 v v 14.8 mv 2 2.127 vdc. error amplifier output (comp) voltage bias point change with load in a closed loop configuration, the comp pin may move in order to maintain the output voltage constant when load current changes. the required change at the comp pin depends partially on the scaling of the current feedback signal as follows: v r s g csa i out n where r s is the current sense resistance in each phase and n is the number of phases. also, when load current changes, nonideal conversion efficiency causes the change in input power to exceed the change in output power, and the duty cycle becomes: d d efficiency and d d d d efficiency (d efficiency) efficiency d (1 efficiency) efficiency peak to peak ripple current therefore also changes by nearly (1 ? efficiency) / efficiency, thereby changing the amplitude of the external ramp by this amount. the complete change required at the comp pin will therefore be: (int_ramp g csa ext_ramp) 2 (1 efficiency ) efficienc y v r s g csa i out n
NCP5318 http://onsemi.com 16 for the converter described above with 4 phases and 85% efficiency at 100 a full load, the error amplifier output changes by: (25 mv 3.0 v v 14.8 mv) 2 (1 0.85) 0.85 v comp 1.0 m 3.0 v v 100 a 4 83 mv additionally, if the ?droop? feature is used, the output voltage change resulting from the synthesized, closed loop output impedance (referred to as the output loadline) is as follows: v r ll i out where r ll is the value, in ohms, of the output loadline. summation of this change at the pwm comparator input forces the error amplifier output voltage to respond with an identical change which always opposes that forced by the sensed current previously described, which reduces the amount of error amplifier output movement required. figure 18 shows the open loop response of the pwm comparator and resulting phase current upon an output voltage dip. before t1, the converter is in steady ? state operation. the inductor current provides a portion of the pwm ramp through the current sense amplifier. the pwm cycle ends when the sum of the current ramp, the ?partial? internal ramp, the offset and the output voltage exceeds the level of the comp pin. at t1, the load current increases and the output voltage sags. the next pwm cycle begins and the cycle continues longer than before until t2, when the current signal has increased enough to make up for the lower voltage at the vfb pin. after t2, the output voltage remains lower, and the average current signal level (csa output) is raised so that the sum of the current and voltage signal is the same as with the original load. in a closed loop system, the comp pin would move higher to restore the output voltage to the original level. swnode v ffb (v out ) internal ramp csa out comp csa output + internal ramp + offset + csxn t1 t2 figure 18. open loop operation
NCP5318 http://onsemi.com 17 inductive current sensing for lossless sensing, current can be measured across the inductor as shown in figure 19. in the diagram, l is the output inductance and r l is the inherent inductor resistance. to compensate the current sense signal, the values of r csx and c csx are chosen so that l/r l = r csx x c csx . if this criteria is met, the current sense signal should be the same shape as the inductor current and the voltage signal between csxp and csxn will represent the instantaneous value of inductor current. also, the circuit can be analyzed as if a sense resistor of value r l was used. when choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. copper magnet wire has a temperature coef ficient of 0.39% per degree c. the increase in winding resistance at higher temperatures should be considered when setting the phase peak current limit threshold. if current sensing more accurate than provided by inductive sensing is required, current can be sensed through a resistor as shown in figure 17. current sharing accuracy for accurate current sharing, the current sense inputs should sense the current at identical points at each phase sense resistance. printed circuit board (pcb) traces that carry inductor cu rrent can be used as part of the current sense resistance by selecting where the current sense signal is picked up along a current carrying trace, but variations of pcb copper base thickness, plating, and etching can degrade current sharing and must be well controlled. the total current sense resistance used for calculations must include any pcb trace resistance that carries inductor current between the csxp input and the csxn input. current sense amplifier (csa) input mismatch and the value of the current sense component will determine the accuracy of the current sharing between phases. the worst case csa input mismatch is 4 mv and will typically be within 1.5 mv. the difference in peak currents between phases will be the csa input mismatch divided by the current sense resistance. if all current sense components are of equal resistance, a 1.5 mv mismatch with a 1.0 m sense resistance will contribute 1.5 a of current difference between phases. figure 19. enhanced v 2 control employing lossless inductive current sensing and internal ramp + ? swnode lx r csx rlx csxp csa cox csxn + v out (v core ) ?fast ? feedback? connection + ? pwm comp to pwm latch reset channel startup offset ? + e.a. dac out v fb comp internal ramp + x = 1, 2, 3 or 4 c csx + ? v ffb external ramp size and current sensing the internal ramp allows flexibility in setting the current sense time constant. typically, the current sense r csx x c csx time constant should be equal to or slightly slower than the inductor?s time constant. if rc is chosen to be smaller (faster) than l/r l , the ac or transient portion of the current sensing signal will be scaled larger than the dc portion. this will provide a larger steady ? state ramp, but transient circuit response will be affected and must be evaluated carefully. the current signal will overshoot during transients and settle at the rate determined by r csx x c csx . it will eventually settle to the correct dc level, but the error will decay with the time constant of r csx x c csx . excessive error can degrade transient response, adaptive positioning (droop) and current limit. during a positive current transient, the comp pin will be required to overshoot in response to the current signal in order to maintain the output voltage. phase pulse ? by ? pulse overcurrent protection will trip earlier than it would if compensated correctly. similarly, the v drp signal will overshoot which will produce too much transient droop in the output voltage, and also result in hiccup ? mode current limit having a lower threshold for fast rising step loads than for slowly rising output currents.
NCP5318 http://onsemi.com 18 transient response and adaptive voltage positioning for applications with fast transient currents, the output filter is frequently sized larger than ripple currents require in order to reduce voltage excursions during load transients. in addition, adaptive voltage positioning can reduce peak ? peak output voltage deviations due to load transients and allow use of a smaller output filter. adaptive voltage positioning sets output voltage higher than nominal at light loads, and output voltage is allowed limited sag when the load current is applied. upon removal of the load, output voltage returns no higher than the original level, allowing one output transient peak to be canceled over a load application and release cycle. for low current applications, a simple dropping resistor in series with the output can provide fast, accurate adaptive positioning. however, at high currents, the loss in a dropping resistor becomes excessive. for example, a 50 a converter with a 1.0 m resistor would provide a 50 mv change in output voltage between no load and full load and would dissipate 2.5 w. lossless adaptive voltage positioning (avp) is an alternative to using a droop resistor. figure 20 shows how avp works. the waveform labeled ?normal? shows a converter without avp. adaptive positioning adaptive positioning normal fast slow limits figure 20. adaptive voltage positioning on the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. with fast (ideal) avp, the peak ? to ? peak excursions are cut in half. in the slow avp waveform, the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. the controller can be configured to adjust the output voltage based on the output current of the converter as shown in the application diagram in fi gure 1. the no ? load positioning is set internally to vid ? 19 mv, reducing the potential error due to resistor and bias current mismatches. in order to realize the avp function, a resistor divider network is connected between v fb , v drp and v out . during no ? load conditions, the v drp pin is at the same voltage as the v fb pin. as the output current increases, the v drp pin voltage increases proportionally. this drives the v fb voltage higher, causing v out to ?droop? according to a loadline set by the resistor divider network. the response during the first few microseconds of a load transient is controlled primarily by power stage output impedance, and by the esr and esl of the output filter. the transition between fast and slow positioning is controlled by the total ramp size and the error amp compensation. if the ramp size is too large or the error amp too slow, there will be a long transition to the final voltage after a transient. this will be most apparent with low capacitance output filters. overvoltage protection overvoltage protection (ovp) in the enhanced v 2 control topology is provided by operation of the synchronous rectifiers. the control loop responds to an overvoltage condition within 40 ns, causing the gatex output to shut off. the (external) mosfet driver should react normally to turn off the top mosfet and turn on the bottom mosfet . this acts quickly to discharge the output voltage and prevent damage to the load. the regulator will remain in this state until the fault latch is reset by cycling power at the v cc pin. if the voltage at the v ffb pin exceeds 200 mv above the vid voltage, the converter will latch off. the ovp circuit begins monitoring the output voltage as soon as the v cc voltage exceeds the uvlo threshold of the part. the ovp circuit is then always active, regardless of operating status. power good according to the latest specifications, the power good (pwrgd) signal must be asserted when the output voltage is within a window defined by the vid code, as shown in figure 21. the pwrls pin is provided to allow the pwrgd comparators to accurately sense the output voltage. the effect of the pwrgd lower threshold can be modified using a resistor divider from the output to pwrls to ground, as shown in figure 22. pwrgd ??? ??? ??? ??? ???? ???? ???? ???? v lower vid + 80 mv v out high low pwrgd ? 2.6 % +2.6% ? 5.0 % +5.0% figure 21. pwrgd assertion window low pwrgd low pwrgd high figure 22. adjusting the pwrgd threshold v out r1 r2 pwrls
NCP5318 http://onsemi.com 19 since the internally ? set thresholds for pwrls are v outno load /2 for the lower threshold and v out no load + 100 mv for the upper threshold, a simple equation can be provided to assist the designer in selecting a resistor divider to provide the desired pwrgd performance. v lower v outnoload 2 r 1 r 2 r 2 v upper v outnoload 100 mv the logic circuitry inside the chip sets pwrgd low only after a delay period has been passed. a ?power bad? event does not cause pwrgd to go low unless it is sustained through the delay time of 1 ms. if the anomaly disappears before the end of the delay, the pwrgd output will never be set low. in order to use the pwrgd pin as specified, the user is advised to connect external resistors as necessary to limit the current into this pin to 4.0 ma or less. undervoltage lockout the NCP5318 includes an undervoltage lockout circuit. this circuit keeps the ic?s output drivers low until v cc applied to the ic reaches 9.0 v. the gate outputs are disabled when v cc drops below 8.0 v. soft ? start at initial power ? up, both ss and comp voltages are zero. the total ss capacitance will begin to charge with a current of 70 a. the error amplifier directly charges the comp capacitance. an internal clamp ensures that the comp pin voltage will always be less than the voltage at the ss pin, ensuring proper startup behavior. all gate outputs are held low until the comp voltage reaches 0.6 v. once this threshold is reached, the gate outputs are released to operate normally. current limit the individual phase currents are summed to compare a total current signal to a user adjustable voltage on the i lim pin. if the i lim voltage is exceeded, the fault latch trips and the converter is latched off. v cc must be recycled to reset the latch. fault protection logic the NCP5318 includes fault protection circuitry to prevent harmful modes of operation from occurring. the fault logic is described in table 1. gate outputs the NCP5318 is designed to operate with external gate drivers. accordingly, the gate outputs are capable of driving a 100 pf load with typical rise and fall times of 5.0 ns. an additional signal, drvon, works in conjunction with the gate outputs. the drvon signal is intended to be used as an enable signal for external gate drivers, such as the ncp3418b. if the drvon signal is low, the gate driver will be disabled and both mosfet s in the synchronous rectified phase channel will be held in the off position. if the drvon signal is high, the gate driver will be enabled. the high side mosfet will be enabled if the gate output is high and drvon is high. the low side mosfet will be enabled if the gate output is low and drvon is high. the drvon signal at power up will initially go high as v cc rises above the power on reset (por) of the ic, roughly 5 v. it will stay high until the v cc voltage exceeds the uvlo threshold of the part. drvon will then go to a low state and stay low until the part is enabled or an ovp is detected. digital to analog converter (dac) the output voltage of the NCP5318 is set by means of a 6 ? bit, 0.5% dac. the vid pins must be pulled high externally. a 1.0 k pullup to a maximum of 3.3 v is recommended to meet intel specifications. to ensure valid logic signals, the designer should ensure at least 800 mv will be present at the ic for a logic high. the output of the dac is described in the electrical characteristics section of the data sheet. these outputs are consistent with vr 10.x and processor specifications. the dac output is equal to the vid code specification minus 19 mv. the latest vr and processor specifications require a power supply to turn its output off in the event of a 1 1111x vid code. when the dac sees such a code, the gate pins stop switching and go low. this condition is described in table 1. table 1. description of fault logic faults results stop switching pwrgd level driver enable ss character- istics reset method overvoltage lockout yes high ? 0.3 ma power on enable low yes depends on output voltage level low ? 0.3 ma not affected module overcurrent limit yes depends on output voltage level low ? 0.3 ma power on dac code = 1 1111x yes depends on output voltage level low ? 0.3 ma change vid code v ref undervoltage lockout yes depends on output voltage level low ? 0.3 ma power on pwrls out of range no low high not affected not affected
NCP5318 http://onsemi.com 20 adjusting the number of phases the NCP5318 is designed with a selectable ? phase architecture. designers may choose any number of phases up to four. the phase delay is automatically adjusted to match the number of phases that will be used. this feature allows the designer to select the number of phases required for a particular application. four ? phase operation is standard. all phases switch with a 90 degree delay between pulses. no special connections are required. three ? phase operation is achieved by disabling phase 4. tie together cs4n and cs4p, and then pull both pins to v cc . the remaining phases will continue to switch, but now there will be a 120 degree delay between phases. the phase firing order will become 1 ? 2 ? 3. two ? and single ? phase operation may be realized as well. first, the designer must choose the proper phases. two phase operation must use phases 2 and 4 by tying cs1n, cs1p, cs3n and cs3p to ground. this will then use phases 2 and 4 to control gate drivers. the other gate control outputs may switch, so leave them unconnected. single phase is best accomplished by using only phase 2 as the switch controller . connect cs2p and cs2n pins to the current sense circuit, and gate control output 2 to the gate driver ic input. tie all other csxx pins together and connect them to ground. design procedure 1. setting the switching frequency the total resistance from r osc to ground sets the operating frequency for all phases of the converter. the frequency can be set for either the three phase or four phase mode by using figure 7, ?oscillator frequency versus total r osc value?. after choosing the desired operating frequency and the number of phases, use the figure to determine the necessary resistance. if two phase operation is desired, use the value given for four phase operation. the voltage from r osc is closely regulated at 1.0 v. this voltage can be used as the reference for the overcurrent limit set point on the i lim pin. design a voltage divider with the appropriate division ratio to give the desired i lim voltage and total resistance to set the operating frequency. since loading by the i lim pin is very small, the frequency selection will not be affected. 2. output capacitor selection the output capacitors filter the current from the output inductors and provide a low impedance for transient load current changes. typically, microprocessor applications require both bulk (polymer, aluminum, or tantalum electrolytic) and low impedance, high frequency (ceramic) types of capacitors. the bulk capacitors provide ?hold up? during transient loading until phase currents ramp up or down. the low impedance capacitors reduce steady ? state ripple voltage and bypass the bulk capacitance for fast output current changes. the designer must determine the number of bulk capacitors so as to meet the peak transient requirements. the formula below can be used to provide a starting point for the minimum number of bulk capacitors (nb out,min ): nb out,min esr per capacitor i o,max v o,max (eq. 1) the esl of the bulk plus ceramic capacitors also affects the voltage change during a load transient according to: i o,max esr nb out,min (eq. 2) v o,max ( i o,max t ) esl where esl is the equivalent esl of all bulk and ceramic output capacitors in parallel. capacitor manufacturers do not always specify the esl of their components and it is affected by the inductance added by the pcb layout. therefore, it is necessary to start a design with slightly more than the minimum number of bulk and ceramic capacitors and perform transient testing to determine the final number of bulk capacitors. intel processor specifications discuss ?dynamicvid? (dvid), by which the vid codes are stepped up or down to a new desired output voltage. timing requirements for when the output must be in regulation further complicates output capacitor selection. the ideal output capacitor selection has low esr and low capacitance. too much output capacitance will make it difficult to meet dvid timing specifications; too much esr will complicate the transient solution. the sanyo 4sepc560 and panasonic eeu ? fl provide a good balance of capacitance vs. esr. microprocessor manufacturers often specify a minimum number of ceramic capacitors, which may need adjustment to meet ripple voltage requirements. the output voltage ripple can be calculated using the output inductor value derived in the following section (l o,min ) and the number of bulk output capacitors (nb out,min ) determined above: v out,p p (esrperbulkcap. nb out,min ) (eq. 3) [ ( v in #phase v out ) d ( l o,min f sw ) ] v in eslperceramiccap. nc out,min
l o,min this formula assumes steady ? state conditions with no more than one phase on at any time. the second term in equation 3 is the total ripple current seen by the output capacitors. the total output ripple current is the ?time summation? of the four individual phase currents that are 90 degrees out ? of ? phase. as the inductor current in one phase ramps upward, current in the other phases ramp downward and provides a canceling of currents during part of the switching cycle. therefore, the total output ripple current and voltage are reduced in a multi ? phase converter.
NCP5318 http://onsemi.com 21 3. output inductor selection the output inductor is a very critical component in the converter because it directly affects the choice of other components and affects both the steady ? state and transient performance of the converter. when selecting an inductor, the designer must consider factors such as dc current, peak current, core loss, magnetic saturation, output voltage ripple, load step and release, temperature, physical size and cost. in general, the output inductance value should be electrically and physically as small as possible in order to provide the best transient response at minimum cost. if a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. on the other hand, lower inductance requires more parallel ceramic output capacitors to make the output filter esl low enough to avoid excessive output voltage ripple. and the higher ripple current in the mosfets and input capacitors increases dissipation and lowers converter efficiency (especially at light loads) ? possibly requiring the use of higher rated mosfets, an oversized thermal solution, and the use of more or higher current rated input capacitors, which increases converter cost. too high a ripple current may saturate the inductor, further increasing ripple current and all losses including core loss. one method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. lower ripple currents will result in less core and mosfet losses and higher converter efficiency. equation 4 may be used to calculate the inductor value to produce a given maximum ripple current ( ) per phase. the inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. conversely, higher inductor values will result in less than the selected maximum ripple current. lo min (v in v out ) v out ( i o,max v in f sw ) (eq. 4) is the ripple current as a percentage of the maximum output current per phase ( = 0.15 for 15%, = 0.25 for 25%, etc.). if the minimum inductor value is used, the inductor current will swing ( /2)% about its value at the center. therefore, for a four ? phase converter, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + /2) ? i o,max /4. the maximum inductor value is limited by the transient response required of the converter. if the converter is to have a fast transient response, the inductor should be made as small as will be allowed by other constraints. if the inductor is too large, its current will change too slowly, the output voltage will droop excessively, more bulk capacitors will be required and the converter cost will be increased. for a given inductor value (l o ), it is useful to determine the time required to increase or decrease the current. for increasing current: t inc lo i o (v in v out ) (eq. 5) for decreasing current: t dec lo i o (v out ) (eq. 6) for typical processor applications with output voltages less than one quarter of the input voltage, the current can be increased more quickly than it can be decreased. thus, it may be more difficult for the converter to avoid overshooting the regulation limits when the load is removed than when it is applied. 4. input capacitor selection input capacitors must be both bulk electrolytic and ceramic types. bulk capacitors are needed to ensure converter stability, and can provide some buffering of the atx power supply from the effects of load step and release. the ceramic capacitors are needed to provide the input ripple current. the choice and number of ceramic input capacitors is primarily determined by their voltage and ripple current ratings. the designer must choose capacitors that will support the worst case input voltage with adequate margin. to calculate the number of input capacitors, the converter rms input ripple current must be calculated by the following procedure: i in,avg i o,max d (eq. 7) where: d is the duty cycle of the converter, d = v out /v in ; is the specified minimum efficiency; i o,max is the maximum converter output current. the input capacitors will discharge when the control fet is on and charge when the control fet is off as shown in figure 23. i c,max i c,min 0 a ? i in,avg control fet on, input caps discharging control fet off, input caps charging t on t/4 i c,in = i c,max ? i c,min figure 23. input capacitor current for a four ? phase converter
NCP5318 http://onsemi.com 22 the following equations will determine the maximum and minimum currents delivered by the input capacitors: i c,max i lo,max i in,avg (eq. 8) i c,min i lo,min i in,avg (eq. 9) i lo,max is the maximum output inductor current: i lo,max i o,max i lo 2 (eq. 10) where is the number of phases in operation. i lo,min is the minimum output inductor current: i lo,min i o,max i lo 2 (eq. 11) i lo is the peak ? to ? peak ripple current in the output inductor of value lo: i lo (v in v out ) d (lo f sw ) (eq. 12) for the four ? phase converter, the input capacitor(s) rms current is then: i cin,rms [4d (i c,min 2 i c,min i c,in i c,in 2 3 ) i in,avg 2 (1 4d)] 1 2 (eq. 13) select the number of input capacitors (nc in ) to provide the rms input current (i cin,rms ) based on the rms ripple current rating per capacitor (i rms,rated ): nc in i cin,rms i rms,rated (eq. 14) for a four ? phase converter with perfect efficiency ( = 1), the worst case input ripple ? current will occur when the converter is operating at a 12.5% duty cycle. at this operating point, the parallel combination of input capacitors must support an rms ripple current equal to 12.5% of the converter?s dc output current. at other duty cycles, the ripple ? current will be less. for example, at a duty cycle of either 6% or 19%, the four ? phase input ripple ? current will be approximately 10% of the converter?s dc output current. in general, capacitor manufacturers require derating to the specified ripple ? current based on the ambient temperature. more capacitors will be required because of the current derating. 5. input inductor selection the use of an inductor between the input capacitors and the power source isolates the voltage source and the system from noise generated by the switching converter, while also reducing the input current slew rate during load transients. the worst case input current slew rate will occur during the first few pwm cycles immediately after a step ? load change is applied as shown in figure 24. when the load is applied, the output voltage is pulled down very quickly. current through the output inductors will not change instantaneously, so the initial transient load current is conducted by the output capacitors. the output voltage will step downward depending on the magnitude of the output current (i o,max ), the per capacitor esr of the output capacitors (esr out ) and the number of bulk electrolytic output capacitors (nb out ) as shown in figure 24. the output voltage at full transient load will be: v out,full ? load (eq. 15) v out,no ? load (i o,max ) esr out nb out when the control mosfet (q1 in figure 24) turns on, the input voltage will be applied to the input terminal of the output inductor (the swnode). at that instant, the voltage across the output inductor can be calculated as: v lo v in v out,full ? load (eq. 16) v in v out,no ? load (i o,max ) esr out nb out the differential voltage across the output inductor will cause its current to increase linearly with time. the slew rate of this current can be calculated from: di lo dt v lo lo (eq. 17)
NCP5318 http://onsemi.com 23 figure 24. calculating the input inductance + + vi 12 v li 470 nh nb in cb in esr in /nb in q2 q1 lo esr out /nb out 60 u(t) nb out cb out vi(t = 0) = 12 v swnode vo(t = 0) = 1.480 v v ci i lo v out i li max di/dt occurs in first few pwm cycles. + ? current changes slowly in the input inductor so the input capacitors must initially deliver most of the input current. the amount of voltage drop across the input capacitors ( v cin ) is determined by the number of bulk input capacitors (nb in ), their per capacitor esr (esr in ) and the current in the output inductor according to: v cin esr in nb in dl lo dt d f sw (eq. 18) before the load is applied, the voltage across the input inductor (v lin ) is very small and the input capacitors charge to the input voltage v in . after the load is applied, the voltage drop across the input capacitors, v cin , appears across the input inductor as well. from this, the minimum value of the input inductor can be calculated from: li min v lin ( di in dt max ) v cin ( di in dt max ) (eq. 19) di in /dt max is the maximum allowable input current slew rate. the input inductance value calculated from equation 19 is relatively conservative. it assumes the supply voltage is very ?stiff? and does not account for any parasitic elements that will limit di/dt such as stray inductance. also, the esr values of the capacitors specified by the manufacturer?s data sheets are worst case high limits. in reality, input voltage ?sag,? lower capacitor esrs and stray inductance will further reduce the slew rate of the input current. as with the output inductor, the input inductor must support the maximum current without saturating. also, for an inexpensive iron powder core, such as the ? 26 or ? 52 from micrometals, the inductance ?swing? with dc bias must be taken into account since inductance will decrease as the dc input current increases. at the maximum input current, the inductance must not decrease below the minimum value or the di/dt will be higher than expected. 6. mosfet and heatsink selection power dissipation, package size and thermal requirements drive mosfet selection. to adequately size the heat sink, the design must first predict the mosfet power dissipation. once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. power dissipation has two primary contributors: conduction losses and switching losses. the control or upper mosfet will display both switching and conduction losses. the synchronous or lower mosfet will exhibit only conduction losses because it switches with nearly zero voltage. however, the body diode in the synchronous mosfet will incur diode losses during the non ? overlap time of the gate drivers. for the upper or control mosfet, the power dissipation can be approximated from: p d,control (i rms,cntl 2 r ds(on) ) (i lo,max q switch i g v in f sw ) ( q oss 2 v in f sw ) (v in q rr f sw ) (eq. 20) the first term represents the conduction or i 2 r losses when the mosfet is on while the second term represents switching off losses. the third term is the loss associated with charging the control and synchronous mosfet output capacitances when the control mosfet turns on. the output losses are caused by the output capacitances of both the control and synchronous mosfet but are dissipated only in the control fet. the fourth term is the loss due to the reverse recovered charge of the body diode in the synchronous mosfet. the first two terms are usually adequate to predict the majority of the losses.
NCP5318 http://onsemi.com 24 i rms,cntl is the rms value of the current in the control mosfet: (eq. 21) i rms,cntl (d (i lo,max 2 i lo,max i lo,min i lo,min 2 3 )) 1 2 i lo,max is the maximum output inductor current: i lo,max i o,max i lo 2 (eq. 22) i lo,min is the minimum output inductor current: i lo,min i o,max i lo 2 (eq. 23) i o,max is the maximum converter output current. d is the duty cycle of the converter: d v out v in (eq. 24) i lo is the peak ? to ? peak ripple current in the output inductor of value l o : i lo (v in v out ) d (lo f sw ) (eq. 25) r ds(on) is the on resistance of the high side mosfet at the applied gate drive voltage. q switch is the post gate threshold portion of the gate ? to ? source charge plus the gate ? to ? drain charge. this may be specified in the data sheet or approximated from the gate ? charge curve as shown in the figure 25. q switch q gs2 q gd (eq. 26) i g is the output current from the gate driver ic. v in is the input voltage to the converter. f sw is the switching frequency of the converter. q rr is the reverse recovery charge of the lower mosfet. q oss is the sum of the high and low side mosfet output charges specified in the data sheets, or estimated from integrating c oss from zero volts to v in . for the lower or synchronous mosfet, the power dissipation can be approximated from: p d,synch (i rms,synch 2 r ds(on) ) (vf diode i o,max t nonoverlap f sw ) (eq. 27) where: vf diode is the forward voltage of the mosfet?s intrinsic diode at the converter output current. t nonoverlap is the non ? overlap time between the upper and lower gate drivers to prevent cross conduction. this time is usually specified in the data sheet for the driver ic. the first term represents the conduction or i 2 r losses when the mosfet is on and the second term represents the diode losses that occur during the gate non ? overlap time. all terms were defined in the previous discussion for the control mosfet with the exception of: (eq. 28) i rms,synch ((1 d) (i lo,max 2 i lo,max i lo,min i lo,min 2 3 )) 1 2 i d v gate v drain q gd q gs2 q gs1 v gs_th figure 25. mosfet switching characteristics when the mosfet power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature. t (t j t a ) p d (eq. 29) where: t is the total thermal impedance ( jc + sa ); jc is the junction ? to ? case thermal impedance of the mosfet; sa is the sink ? to ? ambient thermal impedance of the heatsink assuming direct mounting of the mosfet if no thermal ?pad? is used; t j is the specified maximum allowed junction temperature; t a is the worst case ambient operating temperature. for to ? 220 and to ? 263 packages, standard fr ? 4 copper clad circuit boards will have approximate thermal resistances ( sa ) as shown below: pad size (in 2 /mm 2 ) single ? sided 1 oz. copper 0.50/323 60 ? 65 c/w 0.75/484 55 ? 60 c/w 1.00/645 50 ? 55 c/w 1.50/968 45 ? 50 c/w
NCP5318 http://onsemi.com 25 as with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading and component variations (i.e., worst case mosfet r ds(on) ). also, the inductors and capacitors share the mosfet?s heatsinks and will add heat and raise the temperature of the circuit board and mosfet. for any new design, it is advisable to have as much heatsink area as possible. all too often, new designs are found to be too hot and require re ? design to add heatsinking. 7. error amplifier tuning the high frequency gain of the voltage feedback loop affects transient response and control loop stability. this loop gain can be adjusted by changing the error amplifier?s high frequency gain, which is done by increasing or decreasing the error amplifier output loading capacitor (c amp ). the error amplifier has a transconductance characteristic (amplifier output current is proportional to amplifier input voltage), causing amplifier output voltage to be proportional to amplifier output load impedance. if c amp is too lar ge, the loop gain at high frequencies will be too low, and the converter output voltage may exhibit an underdamped response to a load transient. on the other hand, if c amp is too small, there will be too much loop gain at high frequencies, which may decrease converter output voltage stability. for initial prototype startup, c amp = 10 nf is recommended. when reducing c amp , peak ? to ? peak ripple voltage at the comp pin should remain less than 20 mvp ? p. excessive ripple at the comp pin will contribute to pwm pulse jitter. in general, the lowest loop gain that achieves acceptable transient response should be used. adding a resistor in series with c amp will increase control loop damping in response to load transients as shown in figures 26 and 27, where 1430 was added in series with the 1.8 nf c amp (adaptive voltage positioning not used). figure 26. converter output and comp response to a load step (no droop). 0 in series with c amp figure 27. converter output and comp response to a load step (no droop), resistance in series with c amp current load current, 60 a/div load current, 60 a/div output voltage, 50 mv/div output voltage, 50 mv/div comp voltage, 100 mv/div comp voltage, 100 mv/div 20 s/div 20 s/div
NCP5318 http://onsemi.com 26 8. adaptive voltage positioning two resistors program the adaptive voltage positioning (avp): r fb and r drp . these components form a resistor divider, shown in figures 28 and 29, between v drp , v fb , and v out . ? + + ? r cs1 cs1p c cs1 l1 0 a g vdrp + ? r csx csxp c csx lx 0 a g vdrp comp error amp vid ? 19 mv r drp r fb v drp = vid ? 19 mv v fb = vid ? 19 mv v core i drp = 0 i fb = 0 v core = vid ? 19 mv + ibias vfb r fb figure 28. avp circuitry at no ? load + ? cs1n csxn ? + + ? r cs1 cs1p c cs1 l1 i max /n g vdrp + ? r csx csxp c csx lx i max /n g vdrp comp error amp vid ? 19 mv r drp r fb v drp = vid ? 19 mv + i max ? r l ? g vdrp v fb = vid ? 19 mv v core i drp i fb v core = vid ? 19 mv ? i drp r fb figure 29. avp circuitry at full ? load i drp = i max ? r l ? g vdrp /r drp i fb = i drp = vid ? 19 mv ? i max r l g vdrp r fb /r drp + ? cs1n csxn
NCP5318 http://onsemi.com 27 resistor r fb is connected between v out and the v fb pin of the controller. at no load, this resistor will conduct the very small internal bias current of the v fb pin. therefore r fb should be kept below 10 k to avoid output voltage error due to the input bias current. if the r fb resistor is kept small, the v fb bias current can be ignored. resistor r drp is connected between the v drp and v fb pins of the controller. at no load, v drp , v fb and v out are at the same potential, and no current should flow through r drp or r fb . as load current increases, the voltage at the v drp pin rises. the the r drp and r fb resistors cause the voltage at v out to fall in order to keep the voltage at the v fb pin close to the reference voltage. figure 30 shows the dc effect of avp. ? 0.14 ? 0.06 ? 0.02 0 v out (v) 0 i out (a) 10 60 ? 0.04 ? 0.08 ? 0.10 ? 0.12 20 30 40 50 v out ? vid spec min spec max figure 30. the dc effects of avp vs. load to choose components, select the appropriate resistor ratio based on the desired loadline and sense resistor. at no load, the output voltage is positioned 19 mv below the dac output setting. the output voltage droop will follow the equation: r drp r fb g r sense r ll (eq. 30) where: g = gain of the current sense amplifiers (v/v); r sense = resistance of the sense element (m ); r ll = load line resistance (m ). it is easiest to select a value for r fb and then evaluate the equation to find r drp . r ll is simply the desired output voltage droop divided by the output current. if a sense resistor is used to detect inductor current, then r sense will be the value of the sense resistor. if inductor sensing is used, r sense will be the resistance of the inductor. refer to the discussion on current sensing for further information. depending on inductor esr and the loadline desired, adding a capacitor on the order of 1 nf in parallel with r drp may improve the transient output voltage waveshape. figure 31. output voltage ? no capacitor in parallel with r drp figure 32. output voltage ? 1.2 nf capacitor in parallel with r drp load current, 60 a/div output voltage, 50 mv/div vdrp voltage, 200 mv/div 5 s/div load current, 60 a/div output voltage, 50 mv/div vdrp voltage, 200 mv/div 5 s/div
NCP5318 http://onsemi.com 28 9. current sensing current sensing is used to balance current between different phases, to limit the maximum phase current and to limit the maximum system current. since the current information is a part of the control loop, better stability is achieved if the current information is accurate and noise ? free. the NCP5318 uses differential current sense amplifiers to achieve the best possible performance. two sense lines are routed for each phase, as shown in figure 29. for inductive current sensing, choose the current sense network (r csx , c csx , x = 1, 2, 3 or 4) to satisfy r csx c csx lo r l (eq. 31) where r l is the inductor esr. this will provide an adequate starting point for r csx and c csx . after the converter is constructed, the value of r csx (and/or c csx ) should be fine ? tuned in the lab by observing the v drp signal during a step change in load current. tune the r csx x c csx network by varying r csx to provide a ?square ? wave? at the v drp output pin with maximum rise time and minimal overshoot as shown in figure 35. for resistive current sensing, choose the current sense network (r csx , c csx , x = 1, 2, 3, or 4) to reject noise spikes, but maintain the fidelity of the triangular current waveform. figure 33. v drp tuning waveforms. the rc time constant of the current sense network is too long (slow): v drp and v out respond too slowly. figure 34. v drp tuning waveforms. the rc time constant of the current sense network is too short (fast): v drp and v out both overshoot. load current, 60 a/div output voltage, 50 mv/div vdrp voltage, 500 mv/div 200 s/div vdrp voltage, 200 mv/div 200 s/div load current, 60 a/div output voltage, 50 mv/div figure 35. v drp tuning waveforms. the rc time constant of the current sense network is optimal: v drp and v out respond to the load current quickly without overshooting. vdrp voltage, 200 mv/div 200 s/div load current, 60 a/div output voltage, 50 mv/div
NCP5318 http://onsemi.com 29 10. current limit setting when the output of the current sense amplifier (cox in the block diagram) exceeds the voltage on the i lim pin, the part will latch off. for inductive sensing, the i lim pin voltage should be set based on the inductor?s maximum resistance (r lmax ). the design must consider the inductor?s resistance increase due to current heating and ambient temperature rise. also, depending on the current sense points, the circuit board may add additional resistance. in general, the temperature coefficient of copper is +0.39% per c. if using a current sense resistor (r sense ), the i lim pin voltage should be set based on the maximum value of the sense resistor. for the overcurrent protection to avoid false tripping, the voltage at the i lim pin should be set even higher if the r csx x c csx time constant is set faster than the l o / r l time constant. a step load change may cause the current signal to appear larger than the actual inductor current and trip the current limit at a lower level than desired. the waveforms in figure 36 show a simulation of the current sense signal and the actual inductor current during a positive step in load current with values of l = 500 nh, r l = 1.6 m , r csx = 20 k , and c csx = 0.01 f. in this case, ideal current signal compensation would require v csx to be 31 k. due to the faster than ideal rc time constant, there is an overshoot of 50% and the overshoot decays with a 200 s time constant. with this compensation, the i lim pin threshold must be set more than 50% above the full load current to avoid triggering current limit during a large output load step. figure 36. inductive sensing waveform during a load step with fast rc time constant (50 s/div) the proper i lim pin voltage can be calculated by: v ilim (i ripp ? p (2 #ph) i l ) r l (1 0.004 (t l 25)) g os ilim where: i l = maximum converter current (a) r l = maximum 25 c sense element resistance ( ) g = maximum current sense to i lim gain (see tabulated specs) i ripp ? p = peak ? to ? peak phase ripple current (a) #ph = number of phases t l = inductor temperature at overload ( c) os ilim = maximum i lim offset (see tabulated specs) (v) this voltage can be programmed by a resistor divider from the r osc pin, as shown in figure 37. figure 37. programming the current limit r osc i lim r1 r2 when the NCP5318 is powered up, the r osc pin will be 1.0 v. this allows the user to determine the resistor divider above by: r2 = r total x v lim / 1.0 v r1 = r total ? r2 where r total is determined as in section 1 above.
NCP5318 http://onsemi.com 30 package dimensions 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae ? ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 ? t ? ? z ? ? u ? t?u 0.20 (0.008) z ac t?u 0.20 (0.008) z ab 0.10 (0.004) ac ? ac ? ? ab ? m 8x ? t ? , ? u ? , ? z ? t?u m 0.20 (0.008) z ac 32 lead lqfp case 873a ? 02 issue c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ? ab ? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ? t ? , ? u ? , and ? z ? to be determined at datum plane ? ab ? . 5. dimensions s and v to be determined at seating plane ? ac ? . 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ? ab ? . 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.450 0.750 0.018 0.030 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
NCP5318 http://onsemi.com 31 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP5318/d intel is a registered trademark of intel corporation. v 2 is a trademark of switch power, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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